Invention Grant
- Patent Title: Semiconductor device design method and design apparatus
- Patent Title (中): 半导体器件设计方法及设计装置
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Application No.: US14132428Application Date: 2013-12-18
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Publication No.: US09032351B2Publication Date: 2015-05-12
- Inventor: Hironori Asano
- Applicant: Fujitsu Semiconductor Limited
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Kawasaki
- Agency: Staas & Halsey LLP
- Priority: JP2013-015030 20130130
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A relationship between distance from a back bias control section which outputs a control signal for controlling a back bias of a transistor and an amount of noise in the control signal outputted from the back bias control section is found. An increase of jitter corresponding to the amount of the noise in a clock transmitted on a clock path connected to a circuit section (IP macro) is found on the basis of the relationship between the distance from the back bias control section and the amount of the noise. The circuit section and the clock path are placed on the basis of the increase of the jitter and an allowable jitter value for the circuit section.
Public/Granted literature
- US20140215423A1 SEMICONDUCTOR DEVICE DESIGN METHOD AND DESIGN APPARATUS Public/Granted day:2014-07-31
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