Invention Grant
US09032411B2 Logical extended map to demonstrate core activity including L2 and L3 cache hit and miss ratio
有权
逻辑扩展映射来演示核心活动,包括L2和L3缓存命中和丢失率
- Patent Title: Logical extended map to demonstrate core activity including L2 and L3 cache hit and miss ratio
- Patent Title (中): 逻辑扩展映射来演示核心活动,包括L2和L3缓存命中和丢失率
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Application No.: US12647417Application Date: 2009-12-25
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Publication No.: US09032411B2Publication Date: 2015-05-12
- Inventor: Barry B. Arndt , William M. Buros , Jennifer L. Vargus
- Applicant: Barry B. Arndt , William M. Buros , Jennifer L. Vargus
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Lieberman & Brandsdorfer, LLC
- Main IPC: G06F9/46
- IPC: G06F9/46 ; G06F9/48

Abstract:
A computer system is provided with a processing chip having one or more processor cores, with the processing chip in communication with an operating system having kernel space and user space. Each processor core has multiple core threads to share resources of the core, with each thread managed by the operating system to function as an independent logical processor within the core. A logical extended map of the processor core is created and supported, with the map including each of the core threads indicating usage of the operating system, including user space and kernel space, and cache, memory, and non-memory. An operating system scheduling manager is provided to schedule a routine on the processor core by allocating the routine to different core threads based upon thread availability as demonstrated in the map, and thread priority.
Public/Granted literature
- US20110161969A1 Consolidating CPU - Cache - Memory Access Usage Metrics Public/Granted day:2011-06-30
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