Invention Grant
- Patent Title: Semiconductor-on-insulator with back side support layer
- Patent Title (中): 具有背面支撑层的绝缘体绝缘体
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Application No.: US12836510Application Date: 2010-07-14
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Publication No.: US09034732B2Publication Date: 2015-05-19
- Inventor: Stuart B. Molin , Paul A. Nygaard , Michael A. Stuber
- Applicant: Stuart B. Molin , Paul A. Nygaard , Michael A. Stuber
- Applicant Address: US CA San Diego
- Assignee: Silanna Semiconductor U.S.A., Inc.
- Current Assignee: Silanna Semiconductor U.S.A., Inc.
- Current Assignee Address: US CA San Diego
- Agency: The Mueller Law Office, P.C.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/70 ; H01L27/12 ; H01L21/78 ; H01L21/84 ; H01L23/36 ; H01L23/367 ; H01L29/786 ; H01L21/762 ; H01L23/00

Abstract:
Embodiments of the present invention provide for the provisioning of efficient support to semiconductor-on-insulator (SOI) structures. Embodiments of the present invention may additionally provide for SOI structures with improved heat dissipation performance while preserving the beneficial electrical device characteristics that accompany SOI architectures. In one embodiment, an integrated circuit is disclosed. The integrated circuit comprises a silicon-on-insulator die from a silicon-on-insulator wafer. The silicon on insulator die comprises an active layer, an insulator layer, a substrate, and a strengthening layer. The substrate consists of an excavated substrate region, and a support region, the support region is in contact with the insulator layer. The support region and the strengthening layer are configured to act in combination to provide a majority of a required stabilizing force to the silicon-on-insulator die when it is singulated from the silicon-on-insulator wafer.
Public/Granted literature
- US20110012223A1 SEMICONDUCTOR-ON-INSULATOR WITH BACK SIDE SUPPORT LAYER Public/Granted day:2011-01-20
Information query
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