Invention Grant
US09034734B2 Systems and methods for plasma etching compound semiconductor (CS) dies and passively aligning the dies
有权
用于等离子体蚀刻化合物半导体（CS）的系统和方法模具并被动地对准模具
- Patent Title: Systems and methods for plasma etching compound semiconductor (CS) dies and passively aligning the dies
- Patent Title (中): 用于等离子体蚀刻化合物半导体（CS）的系统和方法模具并被动地对准模具
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Application No.: US13758265Application Date: 2013-02-04
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Publication No.: US09034734B2Publication Date: 2015-05-19
- Inventor: Chee Siong Peh , Chiew Hai Ng , David G. McIntyre
- Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Main IPC: H01L21/46
- IPC: H01L21/46 ; H01L21/78 ; H01L21/301 ; H01L21/44 ; H01L21/48 ; H01L21/50 ; H01L21/76 ; H01L21/30 ; H01L23/544 ; H01L21/302 ; H01L21/683
Abstract:
Methods are provided for using masking techniques and plasma etching techniques to dice a compound semiconductor wafer into dies. Using these methods allows compound semiconductor die to be obtained that have smooth side walls, a variety of shapes and dimensions, and a variety of side wall profiles. In addition, by using these techniques to perform the dicing operations, the locations of features of the die relative to the side walls are ascertainable with certainty such that one or more of the side walls can be used as a passive alignment feature to precisely align one or more of the die with an external device.
Public/Granted literature
- US20140217556A1 METHODS FOR DICING A COMPOUND SEMICONDUCTOR WAFER, AND DICED WAFERS AND DIE OBTAINED THEREBY Public/Granted day:2014-08-07
Information query
IPC分类:
