Invention Grant
US09035351B2 Semiconductor device 有权
半导体器件

Semiconductor device
Abstract:
A semiconductor device having a p base region and an n+ emitter region that come into contact with an emitter electrode and are selectively provided in a surface layer of an n− drift layer. A gate electrode is provided on a portion of the front surface of the n− drift layer which is interposed between the n+ emitter regions, with a gate insulating film interposed therebetween. In some exemplary embodiments, an n+ buffer layer and a p collector layer which have a higher impurity concentration than the n− drift layer are sequentially provided on a surface of the n− drift layer opposite to the front surface on which the n+ emitter region is provided. The impurity concentration of the n+ buffer layer is equal to or greater than 7×1016 cm−3 and equal to or less than 7×1017 cm−3. Accordingly, it is possible to obtain high field decay resistance.
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