Invention Grant
- Patent Title: JFET ESD protection circuit for low voltage applications
- Patent Title (中): JFET ESD保护电路适用于低压应用
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Application No.: US14449283Application Date: 2014-08-01
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Publication No.: US09035363B2Publication Date: 2015-05-19
- Inventor: Robert Newton Rountree
- Applicant: Robert Newton Rountree
- Main IPC: H01L27/085
- IPC: H01L27/085 ; H01L27/02 ; H01L27/092 ; H01L27/06
Abstract:
An electrostatic discharge (ESD) protection circuit is disclosed. The circuit includes a first region having a first conductivity type (410) is formed at a face of a substrate. A gate having a second conductivity type (406) is formed in the substrate beside the first region. A channel having the first conductivity type is formed below the first region adjacent the gate. A second region having the first conductivity type (404) is formed at the face of the substrate beside the gate. A third region having the first conductivity type (430) is formed below the channel and has a greater impurity concentration than the channel.
Public/Granted literature
- US20140339608A1 JFET ESD PROTECTION CIRCUIT FOR LOW VOLTAGE APPLICATIONS Public/Granted day:2014-11-20
Information query
IPC分类:
