Invention Grant
- Patent Title: Method of in-process intralayer yield detection, interlayer shunt detection and correction
- Patent Title (中): 过程中内部产量检测，层间分流检测和校正方法
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Application No.: US12693019Application Date: 2010-01-25
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Publication No.: US09035673B2Publication Date: 2015-05-19
- Inventor: Michael Yu Tak Young , Scott Jong Ho Limb , William S. Wong , Robert A. Street
- Applicant: Michael Yu Tak Young , Scott Jong Ho Limb , William S. Wong , Robert A. Street
- Applicant Address: US CA Palo Alto
- Assignee: Palo Alto Research Center Incorporated
- Current Assignee: Palo Alto Research Center Incorporated
- Current Assignee Address: US CA Palo Alto
- Agency: Fay Sharpe LLP
- Main IPC: G01R31/14
- IPC: G01R31/14 ; G11C29/02 ; G01R31/28 ; H01L21/66 ; G11C29/04
Abstract:
A system and method for in-process yield evaluation and correction in an array type of device are provided. The system and method include measuring electrical resistance between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical resistance to identify at least one of the following: GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects.
Public/Granted literature
- US20110185322A1 METHOD OF IN-PROCESS INTRALAYER YIELD DETECTION, INTERLAYER SHUNT DETECTION AND CORRECTION Public/Granted day:2011-07-28
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