A display device may have a plurality of pixels of a first group connected to a plurality of first gate lines and first common voltage lines and a plurality of pixels of a second group connected to a plurality of second gate lines and second common voltage lines. The display device drives the first common voltage lines and the second common voltage lines in synchronization with a first clock signal; and drives the plurality of first gate lines and the plurality of second gate lines in synchronization with a second clock signal. I-th first and second common voltage lines (i is a positive integer) are driven to one of a first common voltage and a common reference voltage, and (i+1)-th first and second common voltage lines are driven to one of a second common voltage and the common reference voltage.