Invention Grant
- Patent Title: Debug in a multicore architecture
- Patent Title (中): 在多核架构中进行调试
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Application No.: US10941457Application Date: 2004-09-14
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Publication No.: US09038070B2Publication Date: 2015-05-19
- Inventor: Mark David Lippett , Ayewin Oung
- Applicant: Mark David Lippett , Ayewin Oung
- Applicant Address: US CA Mountain View JP Kanagawa
- Assignee: Synopsys, Inc.,Fujitsu Semiconductor Limited
- Current Assignee: Synopsys, Inc.,Fujitsu Semiconductor Limited
- Current Assignee Address: US CA Mountain View JP Kanagawa
- Agency: Fenwick & West LLP
- Main IPC: G06F9/46
- IPC: G06F9/46 ; G06F9/44 ; G06F11/34 ; G06F11/36 ; G06F11/07

Abstract:
According to a first aspect of the present invention, there is provided a method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators indicative of one or more parameters relating to the function and/or identity of a thread or threads comparing at least some of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.
Public/Granted literature
- US20060069953A1 Debug in a multicore architecture Public/Granted day:2006-03-30
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