Invention Grant
- Patent Title: Stacked microelectronic packages having patterned sidewall conductors and methods for the fabrication thereof
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Application No.: US13591969Application Date: 2012-08-22
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Publication No.: US09040387B2Publication Date: 2015-05-26
- Inventor: Zhiwei Gong , Michael B Vincent , Scott M Hayes , Jason R Wright
- Applicant: Zhiwei Gong , Michael B Vincent , Scott M Hayes , Jason R Wright
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR INC.
- Current Assignee: FREESCALE SEMICONDUCTOR INC.
- Current Assignee Address: US TX Austin
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/30
- IPC: H01L21/30 ; H01L23/538 ; H01L21/78 ; H01L23/48 ; H01L23/31 ; H01L23/498 ; H01L21/56 ; H01L25/10 ; H01L23/00

Abstract:
Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.
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