Invention Grant
- Patent Title: Wiring substrate and method of manufacturing the same
- Patent Title (中): 接线基板及其制造方法
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Application No.: US13433680Application Date: 2012-03-29
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Publication No.: US09040832B2Publication Date: 2015-05-26
- Inventor: Yuichiro Shimizu , Ryo Fukasawa
- Applicant: Yuichiro Shimizu , Ryo Fukasawa
- Applicant Address: JP Nagano-shi
- Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
- Current Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
- Current Assignee Address: JP Nagano-shi
- Agency: Kratz, Quintos & Hanson, LLP
- Priority: JP2011-072694 20110329; JP2012-015679 20120127
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H05K3/38 ; H05K1/09 ; H05K3/46 ; H01L21/48 ; H05K3/10

Abstract:
A method of manufacturing a wiring substrate, includes obtaining a laminated body in which a first copper tin alloy layer and a copper layer are arranged in sequence on a first coupling agent layer, on a first insulating resin layer, forming a seed layer on the copper layer, forming a plating resist in which an opening portion is provided on the seed layer, forming a metal plating layer in the opening portion of the plating resist by applying an electroplating that utilizes the seed layer as a plating power feeding path, removing the plating resist, and forming a first wiring layer on the first coupling agent layer by etching the seed layer, the copper layer, and the first copper tin alloy layer while using the metal plating layer as a mask.
Public/Granted literature
- US20120247814A1 WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2012-10-04
Information query
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