Invention Grant
- Patent Title: Three-dimensional integrated circuit with inter-layer vias and intra-layer coupled transistors
- Patent Title (中): 具有层间通孔和层内耦合晶体管的三维集成电路
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Application No.: US14108454Application Date: 2013-12-17
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Publication No.: US09041078B1Publication Date: 2015-05-26
- Inventor: Jam-Wem Lee
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW
- Agency: Lowe Hauptman & Ham, LLP
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L25/11 ; H01L25/00

Abstract:
A circuit comprises a first layer and a second layer separate from the first layer. The first layer comprises a power line, a first transistor coupled to the power line, a second transistor coupled to the power line, and a first line coupling the first transistor and the second transistor. The second layer comprises a ground line, a third transistor coupled to the ground line, a fourth transistor coupled to the ground line, and a second line coupling the third transistor and the fourth transistor. The circuit also comprises an inter-layer interconnect that couples the first transistor and the third transistor. The inter-layer interconnect also couples the second transistor and the fourth transistor.
Public/Granted literature
- US20150171062A1 THREE-DIMENSIONAL INTEGRATED CIRCUIT WITH INTER-LAYER VIAS AND INTRA-LAYER COUPLED TRANSISTORS Public/Granted day:2015-06-18
Information query
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