Invention Grant
US09041078B1 Three-dimensional integrated circuit with inter-layer vias and intra-layer coupled transistors 有权
具有层间通孔和层内耦合晶体管的三维集成电路

Three-dimensional integrated circuit with inter-layer vias and intra-layer coupled transistors
Abstract:
A circuit comprises a first layer and a second layer separate from the first layer. The first layer comprises a power line, a first transistor coupled to the power line, a second transistor coupled to the power line, and a first line coupling the first transistor and the second transistor. The second layer comprises a ground line, a third transistor coupled to the ground line, a fourth transistor coupled to the ground line, and a second line coupling the third transistor and the fourth transistor. The circuit also comprises an inter-layer interconnect that couples the first transistor and the third transistor. The inter-layer interconnect also couples the second transistor and the fourth transistor.
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