A memory includes a semiconductor layer, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film. A first channel region of a first conductivity type is provided on a surface of the semiconductor layer below the gate insulating film. A diffusion layer of a second conductivity type is provided below the first channel region in the semiconductor layer. The diffusion layer contacts a bottom of the first channel region in a direction substantially vertical to a surface of the semiconductor layer. The diffusion layer forms a PN junction with the bottom of the first channel region. A drain of a first conductivity type and a source of a second conductivity type are provided on a side and another side of the first channel region. A sidewall film covers a side surface of the first channel region on a side of the diffusion layer.