Invention Grant
- Patent Title: Memory system and method of controlling memory system
- Patent Title (中): 内存系统和控制内存系统的方法
-
Application No.: US14083860Application Date: 2013-11-19
-
Publication No.: US09042196B2Publication Date: 2015-05-26
- Inventor: Hiroaki Tanaka
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-ku
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: G11C5/14
- IPC: G11C5/14 ; G11C16/30 ; G11C16/04 ; G06F1/32
Abstract:
According to one embodiment, a low power direction received from a host device is delayed for a first predetermined time and is output as a first signal, and an internal state is caused to transition to a low power consumption mode that corresponds to the low power direction when a second predetermined time has elapsed after the first signal is asserted.
Public/Granted literature
- US20150023101A1 MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM Public/Granted day:2015-01-22
Information query
