Invention Grant
US09042492B2 Staggered transmission and reception for reducing latency and memory 有权
交错传输和接收,以减少延迟和内存

Staggered transmission and reception for reducing latency and memory
Abstract:
A demodulator processes a continuous-time signal to generate at a plurality of encoded bits. An inner decoder processes a first subset of bits within the plurality of encoded bits to correct selected ones of the first subset of bits to form a corrected first subset of bits and to generate partially corrected data from the plurality of encoded bits based on the corrected first subset of bits. An outer decoder processes the partially decoded data, to correct selected ones of a second subset of the plurality of encoded bits to form a corrected second subset of bits. A bit combiner generates data estimates by combining the corrected first subset of bits and the corrected second subset of bits.
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