Invention Grant
US09042737B2 Clock and data recovery unit and power control method therefor and PON system
有权
时钟和数据恢复单元及其功率控制方法和PON系统
- Patent Title: Clock and data recovery unit and power control method therefor and PON system
- Patent Title (中): 时钟和数据恢复单元及其功率控制方法和PON系统
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Application No.: US13985128Application Date: 2012-02-21
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Publication No.: US09042737B2Publication Date: 2015-05-26
- Inventor: Naruto Tanaka
- Applicant: Naruto Tanaka
- Applicant Address: JP Osaka-shi, Osaka
- Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
- Current Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
- Current Assignee Address: JP Osaka-shi, Osaka
- Agency: Drinker Biddle & Reath LLP
- Priority: JP2011-041254 20110228
- International Application: PCT/JP2012/054094 WO 20120221
- International Announcement: WO2012/117890 WO 20120907
- Main IPC: H04B10/00
- IPC: H04B10/00 ; H04L7/00 ; H03L7/08 ; H04B10/272 ; H04J3/06 ; H04W52/02 ; H04L7/033 ; H04J14/02

Abstract:
In the present invention, wasted power consumption caused when a clock and data recovery unit in an optical network unit in a PON system is activated from a power-saving state is reduced and rapid, secure communication is performed. A clock and data recovery unit includes a phase-locked loop that can be set to normal mode or power-saving mode and that includes a voltage-controlled oscillator and recovers a clock signal and a data signal from input signals. The clock and data recovery unit includes a reference clock multiplier circuit that multiplies a reference clock signal and outputs the multiplied reference clock signal; and a frequency training loop that includes the same voltage-controlled oscillator and performs synchronous oscillation training by the voltage-controlled oscillator using the reference clock multiplier circuit before the phase-locked loop transitions from power-saving mode to normal mode.
Public/Granted literature
- US20130322880A1 CLOCK AND DATA RECOVERY UNIT AND POWER CONTROL METHOD THEREFOR AND PON SYSTEM Public/Granted day:2013-12-05
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