Invention Grant
US09043662B2 Double data rate memory physical interface high speed testing using self checking loopback
有权
双数据速率存储器物理接口高速测试使用自检环回
- Patent Title: Double data rate memory physical interface high speed testing using self checking loopback
- Patent Title (中): 双数据速率存储器物理接口高速测试使用自检环回
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Application No.: US12413928Application Date: 2009-03-30
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Publication No.: US09043662B2Publication Date: 2015-05-26
- Inventor: John W. Selking
- Applicant: John W. Selking
- Applicant Address: US CA San Jose
- Assignee: CADENCE DESIGN SYSTEMS, INC.
- Current Assignee: CADENCE DESIGN SYSTEMS, INC.
- Current Assignee Address: US CA San Jose
- Agency: Sawyer Law Group, P.C.
- Main IPC: G11C29/02
- IPC: G11C29/02 ; G01R31/317 ; G01R31/319 ; G11C29/04 ; G11C11/401
Abstract:
A double data rate memory physical interface having self checking loopback logic on-chip is disclosed. Disposed on the chip is a first linear feedback shift register, which is capable of generating a set of test data values that comprise at least two data bits. Also disposed on the chip is a second linear feedback shift register. The second linear feedback shift register is capable of generating a set of expected data values that match the test data values. Further, an internal loopback error check element is disposed on the chip. The internal loopback error check element is used to compare the set of expected data values with the set of test data values.
Public/Granted literature
- US20100251042A1 DOUBLE DATA RATE MEMORY PHYSICAL INTERFACE HIGH SPEED TESTING USING SELF CHECKING LOOPBACK Public/Granted day:2010-09-30
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