A system on chip comprises a bus electrically connected with a master intellectual property (IP) block, a slave IP block, and a default slave IP block. An IP block control part is configured to generate a control signal for activating or inactivating the slave IP block. When a call signal on the slave IP block is received from the master IP block, the bus is configured to transfer the received call signal to either one of the slave IP block and the default slave IP block according to the received call signal and the control signal.