Invention Grant
- Patent Title: Superjunction transistor with implantation barrier at the bottom of a trench
- Patent Title (中): 在沟槽底部具有注入势垒的超结晶体管
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Application No.: US13661935Application Date: 2012-10-26
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Publication No.: US09048115B2Publication Date: 2015-06-02
- Inventor: Tsung-Hsiung Lee , Shang-Hui Tu , Gene Sheu , Neelam Agarwal , Karuna Nidhi , Chia-Hao Lee , Rudy Octavius Sihombing
- Applicant: Vanguard International Semiconductor Corporation
- Applicant Address: TW Hsinchu
- Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
- Current Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
- Current Assignee Address: TW Hsinchu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/08 ; H01L21/265 ; H01L29/66 ; H01L29/06 ; H01L29/417 ; H01L29/10
Abstract:
A method for fabricating a semiconductor device is provided. An epitaxial layer is grown on a substrate, wherein the epitaxial layer and the substrate have a first conductivity type. A trench is formed in the epitaxial layer. A barrier region is formed at a bottom of the trench. A doped region of a second conductivity type is formed in the epitaxial layer and surrounds sidewalls of the trench, wherein the barrier region prevents a dopant used for forming the doped region from reaching the epitaxial layer under the barrier region. The trench is filled with a dielectric material. A pair of polysilicon gates is formed on the epitaxial layer and on both sides of the trench.
Public/Granted literature
- US20140117436A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Public/Granted day:2014-05-01
Information query
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