Invention Grant
- Patent Title: Methods of fabricating three dimensional semiconductor memory devices
- Patent Title (中): 制造三维半导体存储器件的方法
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Application No.: US14281482Application Date: 2014-05-19
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Publication No.: US09048138B2Publication Date: 2015-06-02
- Inventor: Hui-Chang Moon , Sung-Min Hwang , Woonkyung Lee
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Lee & Morse, P.C.
- Priority: KR10-2010-0102559 20101020
- Main IPC: H01L21/3205
- IPC: H01L21/3205 ; H01L21/4763 ; H01L27/115 ; H01L29/792

Abstract:
A three dimensional semiconductor memory device has a stacked structure including cell gates stacked therein that are insulated from each other and first string selection gates laterally separated from each other, vertical active patterns extending through the first string selection gates, multi-layered dielectric layers between sidewalls of the vertical active patterns and the cell gates and between the sidewalls of the vertical active patterns and the first string selection gates, and at least one first supplement conductive pattern. The first string selection gates are disposed over an uppermost cell gate of the cell gates. Each vertical active pattern extends through each of the cell gates stacked under the first string selection gates. The first supplement conductive pattern is in contact with a sidewall of one of the first string selection gates.
Public/Granted literature
- US20140256101A1 METHODS OF FABRICATING THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES Public/Granted day:2014-09-11
Information query
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