Invention Grant
- Patent Title: Integrated circuit package system employing wafer level chip scale packaging
- Patent Title (中): 集成电路封装系统采用晶圆级芯片级封装
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Application No.: US12709425Application Date: 2010-02-19
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Publication No.: US09048197B2Publication Date: 2015-06-02
- Inventor: Byung Tai Do , Heap Hoe Kuan
- Applicant: Byung Tai Do , Heap Hoe Kuan
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Ltd.
- Current Assignee: STATS ChipPAC Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Main IPC: H01L23/22
- IPC: H01L23/22 ; H01L23/52 ; H01L29/40 ; H01L23/02 ; H01L23/31 ; H01L21/56 ; H01L21/683 ; H01L23/544 ; H01L23/00
Abstract:
An integrated circuit package system that includes: providing a substrate with a protective coating; attaching a labeling film to a support member in a separate process; joining the protective coating and the labeling film; and dicing the substrate, the protective coating, and the labeling film to form the integrated circuit package system.
Public/Granted literature
- US20100148355A1 INTEGRATED CIRCUIT PACKAGE SYSTEM EMPLOYING WAFER LEVEL CHIP SCALE PACKAGING Public/Granted day:2010-06-17
Information query
IPC分类:
