A chip package structure includes a package body, a first lead and a second lead. Elements embedded inside the package body include a core circuit having at least one first connection terminal, at least one ESD protection circuit having at least one second connection terminal, at least one third connection terminal and at least one interconnection structure. The interconnection structure is electrically connected to the second connection terminal and the third connection terminal. The first lead on the package body is electrically connected to the second connection terminal and an external circuit. The second lead on the package body electrically connects the first connection terminal and the third connection terminal. The second lead and the first lead are separate in structure.