Disclosed is a semiconductor device provided with an active element in a multilayer interconnect layer and decreased in a chip area. A second interconnect layer is provided over a first interconnect layer. A first interlayer insulating layer is provided in the first interconnect layer. A semiconductor layer is provided in a second interconnect layer and in contact with the first interlayer insulating layer. A gate insulating film is provided over the semiconductor layer. A gate electrode is provided over the gate insulating film. At least two first vias are provided in the first interconnect layer and in contact by way of upper ends thereof with the semiconductor layer.