Method of fabricating multiple gate stack compositions

Invention Grant

US09048335B2 Method of fabricating multiple gate stack compositions 有权

Title translation: 制造多个栅叠层组合物的方法

Please log in to see more content

Patent Title: Method of fabricating multiple gate stack compositions
Patent Title (中): 制造多个栅叠层组合物的方法
Application No.: US13782720

Application Date: 2013-03-01
Publication No.: US09048335B2

Publication Date: 2015-06-02
Inventor: Po-Nien Chen , Eric Huang , Chi-Hsun Hsieh , Wei Cheng Wu , Bao-Ru Young , Harry Hak-Lay Chuang
Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
Applicant Address: TW Hsin-Chu
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
Current Assignee Address: TW Hsin-Chu
Agency: Haynes and Boone, LLP
Main IPC: H01L21/8234
IPC: H01L21/8234 ; H01L27/088

Method of fabricating multiple gate stack compositions

Abstract:

An integrated circuit having multiple different device gate configurations and a method for fabricating the circuit are disclosed. An exemplary embodiment of forming the circuit includes receiving a substrate having a first device region, a second device region, and a third device region. A first interfacial layer is formed over at least a portion of each of the first device region, the second device region, and the third device region. The first interfacial layer is patterned to define a gate stack within the third device region. A second interfacial layer is formed over at least a portion of the second device region. The second interfacial layer is patterned to define a gate stack within the second device region. A third interfacial layer is formed over at least a portion of the first device region. The third interfacial layer defines a gate stack within the first device region.

Abstract(Chinese):

公开了一种具有多个不同器件栅极配置的集成电路及其制造方法。形成电路的示例性实施例包括接收具有第一器件区域，第二器件区域和第三器件区域的衬底。在第一器件区域，第二器件区域和第三器件区域中的每一个的至少一部分上形成第一界面层。图案化第一界面层以在第三器件区域内限定栅极堆叠。在第二装置区域的至少一部分上形成第二界面层。图案化第二界面层以在第二装置区域内限定栅极堆叠。在第一装置区域的至少一部分上形成第三界面层。第三界面层限定第一装置区域内的栅极堆叠。

Public/Granted literature

US20140246732A1 Circuit Incorporating Multiple Gate Stack Compositions Public/Granted day:2014-09-04

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺