Invention Grant
US09048337B2 Vertical transistor, memory cell, device, system and method of forming same 有权
垂直晶体管,存储单元,器件,系统及其形成方法

Vertical transistor, memory cell, device, system and method of forming same
Abstract:
A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is formed in the semiconductor substrate and a body region and a second source/drain region are formed within the semiconductor pillar. A first gate is coupled to a first side of the semiconductor pillar for coupling the first and second source/drain regions together when activated. The vertical memory cell also includes a storage capacitor formed on an extended end of the semiconducting pillar and electrically coupled to the second source/drain region.
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