Invention Grant
- Patent Title: ESD protection scheme using I/O pads
- Patent Title (中): 使用I / O焊盘的ESD保护方案
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Application No.: US13675547Application Date: 2012-11-13
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Publication No.: US09048655B2Publication Date: 2015-06-02
- Inventor: Qingchao Meng , Lei Pan , Shao-Yu Chou
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Associates, LLC
- Priority: CN201210421461 20121029
- Main IPC: H02H9/00
- IPC: H02H9/00 ; H02H9/04 ; H01C7/12 ; H02H1/00 ; H02H1/04 ; H02H3/22 ; H02H9/06

Abstract:
Some embodiments relate to an IC that includes an ESD-susceptible circuit. The IC includes a number of IC pads that are electrically coupled to respective nodes on the ESD-susceptible circuit. The IC pads are electrically accessible from external to the IC, and include one or more power supply pads and one or more I/O pads. The IC also includes a number of ESD protection devices coupled to the plurality of IC pads, respectively. A trigger circuit on the IC is configured to detect an ESD event impingent on a power supply pad and, in response to the detection, to trigger concurrent shunting of energy of the ESD event over both an ESD clamp element of an I/O pad and an ESD clamp element of the power supply pad. Other embodiments are also disclosed.
Public/Granted literature
- US20140118869A1 ESD Protection Scheme Using I/O Pads Public/Granted day:2014-05-01
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