Invention Grant
- Patent Title: Zero-latency network on chip (NoC)
- Patent Title (中): 零延迟网络芯片(NoC)
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Application No.: US12579346Application Date: 2009-10-14
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Publication No.: US09049124B2Publication Date: 2015-06-02
- Inventor: Jean-Jacques Lecler , Philippe Boucard
- Applicant: Jean-Jacques Lecler , Philippe Boucard
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Technologies, Inc.
- Current Assignee: QUALCOMM Technologies, Inc.
- Current Assignee Address: US CA San Diego
- Agency: Muncy, Geissler, Olds & Lowe, P.C.
- Priority: FR0957137 20091013
- Main IPC: G06F3/00
- IPC: G06F3/00 ; H04L12/28 ; H04L12/801 ; H04L12/709 ; H04L12/933 ; G06F13/40

Abstract:
Packet format configurability is extended for packets transported on physical links of an Intellectual Property (IP) core interconnect by using at least two independent parameters: one parameter governing data-width and one parameter governing latency penalty. The at least two independent parameters allow creation of transport protocol packets without additional latency insertion, which is useful for low-latency applications. The at least two independent parameters also allow creation of narrow packets with multi-cycle additional latency, which is useful for latency tolerant, area sensitive applications.
Public/Granted literature
- US20110085550A1 Zero-latency network on chip (NoC) Public/Granted day:2011-04-14
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