Invention Grant
US09049791B2 Terminations and couplings between chips and substrates 有权
芯片和基板之间的端接和耦合

Terminations and couplings between chips and substrates
Abstract:
A method of attaching a chip to the substrate with an outer layer consisting of via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method consisting of optionally removing an organic varnish, positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and applying heat to melt the solder bumps and to wet the ends of the vias with solder.
Public/Granted literature
Information query
Patent Agency Ranking
0/0