Invention Grant
- Patent Title: Inspection apparatus and inspection method for semiconductor device
- Patent Title (中): 半导体器件的检查装置和检查方法
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Application No.: US13784334Application Date: 2013-03-04
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Publication No.: US09052187B2Publication Date: 2015-06-09
- Inventor: Naoyuki Komuta , Masatoshi Fukuda
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Patterson & Sheridan, LLP
- Priority: JP2012-064451 20120321
- Main IPC: G01B11/00
- IPC: G01B11/00 ; G01B11/14 ; G01B11/26 ; G01C1/00 ; G01B11/27 ; H01L23/00

Abstract:
An apparatus relating to the manufacture of stacked semiconductor devices includes, for example, a first holding section configured to hold a first semiconductor device and a second holding section configured to hold a second semiconductor device. Additionally, a measuring section including an imaging device for acquiring images of the first and second semiconductor devices and a control section configured to control the holding sections to correct misalignment between the semiconductor devices. The control section is further configured to determine misalignment using the images of the first and second semiconductor devices when the images include a first alignment mark disposed proximate to an edge of the first semiconductor device and a second alignment mark disposed proximate to an edge of the second semiconductor device.
Public/Granted literature
- US20130250298A1 INSPECTION APPARATUS AND INSPECTION METHOD FOR SEMICONDUCTOR DEVICE Public/Granted day:2013-09-26
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