A multi-level interconnect apparatus includes a substrate including a substrate body having a first side and a second side opposite the first side, a processing unit disposed on the second side of the substrate body, a first input/output (I/O) unit disposed on the first side of the substrate body and configured to be electrically communicable with the processing unit along a thickness dimension of the substrate body and a second I/O unit disposed on the second side of the substrate body and configured to be electrically communicable with the processing unit along a planar dimension of the substrate body.