Invention Grant
- Patent Title: Cache coherence directory in multi-processor architectures
- Patent Title (中): 多处理器架构中的缓存一致性目录
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Application No.: US13877422Application Date: 2012-09-14
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Publication No.: US09053057B2Publication Date: 2015-06-09
- Inventor: Yan Solihin
- Applicant: Yan Solihin
- Applicant Address: US DE Wilmington
- Assignee: Empire Technology Development LLC
- Current Assignee: Empire Technology Development LLC
- Current Assignee Address: US DE Wilmington
- Agency: Moritt Hock & Hamroff LLP
- Agent Steven S. Rubin, Esq.
- International Application: PCT/US2012/055502 WO 20120914
- International Announcement: WO2014/042649 WO 20140320
- Main IPC: G06F12/12
- IPC: G06F12/12 ; G06F12/08

Abstract:
Technologies are generally described for a cache coherence directory in multi-processor architectures. In an example, a directory in a die may receive a request for a particular block. The directory may determine a block aging threshold relating to a likelihood that data blocks, including the particular data block, are stored in one or more caches in the die. The directory may further analyze a memory to identify a particular cache indicated as storing the particular data block and identify a number of cache misses for the particular cache. The directory may identify a time when an event occurred for the particular data block and determine whether to send the request for the particular data block to the particular cache based on the aging threshold, the time of the event, and the number of cache misses.
Public/Granted literature
- US20140082297A1 CACHE COHERENCE DIRECTORY IN MULTI-PROCESSOR ARCHITECTURES Public/Granted day:2014-03-20
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