Invention Grant
- Patent Title: Inhibiting pillars in 3D memory devices
- Patent Title (中): 在3D存储设备中抑制支柱
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Application No.: US13869710Application Date: 2013-04-24
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Publication No.: US09053797B2Publication Date: 2015-06-09
- Inventor: Koji Sakui
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: G11C16/12
- IPC: G11C16/12
Abstract:
Methods and controllers for programming a memory are provided. In one such method, a potential for pillars of the memory that are to be inhibited is lowered, and programming cells of the memory is accomplished while the pillars of the memory that are to be inhibited have the lower potential.
Public/Granted literature
- US20140321215A1 INHIBITING PILLARS IN 3D MEMORY DEVICES Public/Granted day:2014-10-30
Information query
