A method for forming a unit layout pattern includes: forming first through third active regions in the unit layout pattern, each of the first through third active regions aligning and extending along a length in a first direction and having a width in a second direction perpendicular to the first direction; forming first and second gate regions on the first and second active regions, the first and second gate regions electrically connected to each other; forming the first active region of a first conductive type within a second conductive type well region; forming the second active region of a second conductive type; and forming the third active region connected with the first and second gate regions to form a junction diode, the third active region being located between the first or the second active region and an end of the length in the first direction of the unit pattern.