Invention Grant
- Patent Title: Semiconductor package structure and manufacturing method thereof
- Patent Title (中): 半导体封装结构及其制造方法
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Application No.: US13655434Application Date: 2012-10-18
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Publication No.: US09053968B2Publication Date: 2015-06-09
- Inventor: Shih-Wen Chou
- Applicant: ChipMOS Technologies Inc.
- Applicant Address: TW Hsinchu
- Assignee: ChipMOS Technologies Inc.
- Current Assignee: ChipMOS Technologies Inc.
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Priority: TW101101779A 20120117
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L25/10 ; H01L23/13 ; H01L23/31 ; H01L21/56

Abstract:
A method of manufacturing a semiconductor package structure is provided. A supporting plate and multiple padding patterns on an upper surface of the supporting plate define a containing cavity. Multiple leads electrically insulated from one another are formed on the padding patterns, extend from top surfaces of the padding patterns along side surfaces to the upper surface and are located inside the containing cavity. A chip is mounted inside the containing cavity, electrically connected to the leads. A molding compound is formed to encapsulate at least the chip, a portion of the leads and a portion of the supporting plate, fill the containing cavity and gaps among the padding patterns, and exposes a portion of the leads on the top surface. The supporting plate is removed to expose a back surface of each padding pattern, a bottom surface of the molding compound and a lower surface of each lead.
Public/Granted literature
- US20130181333A1 SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Public/Granted day:2013-07-18
Information query
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