Invention Grant
- Patent Title: Through silicon via keep out zone formation method and system
- Patent Title (中): 通过硅通过防区形成方法和系统
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Application No.: US14057951Application Date: 2013-10-18
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Publication No.: US09054166B2Publication Date: 2015-06-09
- Inventor: Cheng-Chieh Hsieh , Hung-An Teng , Shang-Yun Hou , Shin-Puu Jeng
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/768 ; H01L23/48

Abstract:
Keep out zones (KOZ) are formed for a through silicon via (TSV). A device can be placed outside a first KOZ of a TSV determined by a first performance threshold so that a stress impact caused by the TSV to the device is less than a first performance threshold while the first KOZ contains only those points at which a stress impact caused by the TSV is larger than or equal to the first performance threshold. A second KOZ for the TSV can be similarly formed by a second performance threshold. A plurality of TSVs can be placed in a direction that the KOZ of the TSV has smallest radius to a center of the TSV, which may be in a crystal orientation [010] or [100]. A plurality of TSV stress plug can be formed at the boundary of the overall KOZ of the plurality of TSVs.
Public/Granted literature
- US20140045332A1 Through Silicon Via Keep Out Zone Formation Method and System Public/Granted day:2014-02-13
Information query
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