Invention Grant
US09054215B2 Patterning of vertical nanowire transistor channel and gate with directed self assembly
有权
垂直纳米线晶体管沟道和栅极的定向自组装图案化
- Patent Title: Patterning of vertical nanowire transistor channel and gate with directed self assembly
- Patent Title (中): 垂直纳米线晶体管沟道和栅极的定向自组装图案化
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Application No.: US13719113Application Date: 2012-12-18
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Publication No.: US09054215B2Publication Date: 2015-06-09
- Inventor: Paul A. Nyhus , Swaminathan Sivakumar
- Applicant: Paul A. Nyhus , Swaminathan Sivakumar
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L29/78 ; H01L29/775 ; H01L29/66 ; B82Y10/00 ; B82Y40/00 ; H01L29/423 ; H01L29/06 ; H01L29/16
Abstract:
Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.
Public/Granted literature
- US20140170821A1 PATTERNING OF VERTICAL NANOWIRE TRANSISTOR CHANNEL AND GATE WITH DIRECTED SELF ASSEMBLY Public/Granted day:2014-06-19
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