Invention Grant
- Patent Title: Boosting circuit
- Patent Title (中): 升压电路
-
Application No.: US13779220Application Date: 2013-02-27
-
Publication No.: US09054683B2Publication Date: 2015-06-09
- Inventor: Masaya Murata , Tomohiro Oka
- Applicant: Seiko Instruments Inc.
- Applicant Address: JP Chiba
- Assignee: SEIKO INSTRUMENTS INC.
- Current Assignee: SEIKO INSTRUMENTS INC.
- Current Assignee Address: JP Chiba
- Agency: Brinks Gilson & Lione
- Priority: JP2012-053556 20120309
- Main IPC: H03K5/12
- IPC: H03K5/12 ; G11C5/14 ; G11C8/08 ; G11C16/30 ; H02M3/07 ; H02M1/36

Abstract:
A boosting circuit is provided which performs an appropriate boosting operation in accordance with load capacitance. In the boosting circuit, a slope control circuit is provided between a limiter circuit, which limits a high voltage obtained by a charge pump circuit to a desired boosted voltage VPP, and a discharge circuit, which makes the boosted voltage VPP drop quickly to a power supply voltage VCC after the completion of writing, to enable a boosting operation in an appropriate boosted-voltage reach time, by increasing the time taken to reach the boosted voltage VPP in the case where the load capacitance is low, while keeping the time taken to reach the boosted voltage VPP unchanged, irrespective of the presence/absence of the slope control circuit, in the case where the load capacitance is high as in the case of selecting the memory cells collectively.
Public/Granted literature
- US20130234768A1 BOOSTING CIRCUIT Public/Granted day:2013-09-12
Information query
IPC分类: