An information processing device of the invention has a first board on which a tamper detection pattern is installed, a second board that is arranged to face the first board and on which a tamper detection pattern is installed, and sidewalls that are arranged between the first and second boards and along the outer periphery of the first and second boards and that include a plurality of layers (41 and 43) upon which electrodes (33 and 34) for tamper detection are provided. A circuit that needs to be tamper proof is provided in the space that is enclosed by the first and second boards and the sidewalls. The sidewalls have a structure in which electrodes (34) in one layer (43) of the two layers (41 and 43) that are adjacent with an insulating layer (42) interposed there between are arranged at positions corresponding to the spaces between the electrodes provided in the other layer (41).