Invention Grant
US09071248B2 MOS transistor drain-to-gate leakage protection circuit and method therefor
有权
MOS晶体管漏极 - 漏极保护电路及其方法
- Patent Title: MOS transistor drain-to-gate leakage protection circuit and method therefor
- Patent Title (中): MOS晶体管漏极 - 漏极保护电路及其方法
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Application No.: US12811804Application Date: 2010-03-03
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Publication No.: US09071248B2Publication Date: 2015-06-30
- Inventor: Thierry Sicard , Laurent Guillot
- Applicant: Thierry Sicard , Laurent Guillot
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Sherry W. Schumm
- International Application: PCT/IB2010/001110 WO 20100303
- Main IPC: G05F1/00
- IPC: G05F1/00 ; H03K17/687
Abstract:
A circuit having an active mode and a sleep mode includes a power transistor, an amplifier, and a protection circuit. The power transistor has a first current electrode coupled to a first power supply terminal, a second current electrode as an output of the circuit for coupling to a load, and a control electrode, wherein the power transistor is characterized by having a threshold voltage and a leakage current, wherein the leakage current occurs between the control electrode and the first current electrode during the sleep mode. The amplifier has an output coupled to the control electrode of the power transistor that provides an active output during the active mode. The protection circuit detects the leakage current and prevents the leakage current from developing a voltage on the control electrode of the power transistor that exceeds the threshold voltage of the power transistor.
Public/Granted literature
- US20120326690A1 MOS TRANSISTOR DRAIN-TO-GATE LEAKAGE PROTECTION CIRCUIT AND METHOD THEREFOR Public/Granted day:2012-12-27
Information query
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