Invention Grant
- Patent Title: Dynamic error handling using parity and redundant rows
- Patent Title (中): 使用奇偶校验和冗余行的动态错误处理
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Application No.: US13327845Application Date: 2011-12-16
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Publication No.: US09075741B2Publication Date: 2015-07-07
- Inventor: Altug Koker , Shailesh Shah , Aditya Navale , Murali Ramadoss , Satish K. Damaraju
- Applicant: Altug Koker , Shailesh Shah , Aditya Navale , Murali Ramadoss , Satish K. Damaraju
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Thomas R. Lane
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/10 ; H03M13/09 ; H04L1/00 ; H03M13/11

Abstract:
Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.
Public/Granted literature
- US20130159820A1 DYNAMIC ERROR HANDLING USING PARITY AND REDUNDANT ROWS Public/Granted day:2013-06-20
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