Invention Grant
US09075941B2 Method for optimizing electrodeposition process of a plurality of vias in wafer
有权
用于优化晶片中多个通孔的电沉积工艺的方法
- Patent Title: Method for optimizing electrodeposition process of a plurality of vias in wafer
- Patent Title (中): 用于优化晶片中多个通孔的电沉积工艺的方法
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Application No.: US13894420Application Date: 2013-05-14
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Publication No.: US09075941B2Publication Date: 2015-07-07
- Inventor: Yaofeng Sun , Bin Xie , Xunqing Shi , Ou Dong
- Applicant: Hong Kong Applied Science and Technology Research Institute Company Limited
- Applicant Address: CN Hong Kong Science Park, Shatin, New Territories, Hong Kong
- Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
- Current Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
- Current Assignee Address: CN Hong Kong Science Park, Shatin, New Territories, Hong Kong
- Agency: Ella Cheong Hong Kong
- Agent Sam T. Yip
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
The presently claimed invention provides a method for optimizing an electrodeposition process of a plurality of vias in a wafer. Instead of simulating a large number of via on the wafer for via filling, a representative via is selected with the maximum value of critical factor, which is a function of process parameters. The filling of the representative via is simulated with different sampling points to find out the filling goodness in order to find out the optimized process windows of process parameters. An optimizer is also disclosed, which either provides sampling points or reduces sampling points under artificial neural network method. Calculation of filling goodness is used for evaluating via filling quality and further comparing among via fillings simulated at different sampling points. Consequently, the method of present invention is able to shorten the simulation time for via filling as well as provide a process window with high accuracy.
Public/Granted literature
- US20140343901A1 Method for Optimizing Electrodeposition Process of a Plurality of Vias in Wafer Public/Granted day:2014-11-20
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