Memory system controllers can include non-volatile memory control circuitry including a plurality of channel control circuits. Each of the plurality of channel control circuits can be configured to be coupled to a respective number of logical units (LUNs). Memory management circuitry can be coupled to the non-volatile memory control circuitry and configured to allocate a write block cluster for host writes based on an information width of a host bus and a protocol of the host bus. The write block cluster can include one block from fewer than all of the LUNs.