Invention Grant
- Patent Title: Stacked semiconductor die with continuous conductive vias
- Patent Title (中): 具有连续导电通孔的堆叠半导体芯片
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Application No.: US13268580Application Date: 2011-10-07
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Publication No.: US09076664B2Publication Date: 2015-07-07
- Inventor: Perry H. Pelley , Kevin J. Hess , Michael B. McShane
- Applicant: Perry H. Pelley , Kevin J. Hess , Michael B. McShane
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L25/065

Abstract:
A stacked semiconductor device includes a first, a second, a third, and a fourth semiconductor device. A first major surface of each of the first and second semiconductor devices which includes the active circuitry directly face each other, and a first major surface of each of the third and fourth semiconductor devices which includes the active circuitry directly face each other. A second major surface of the second semiconductor device directly faces a second major surface of the third semiconductor device. The stacked semiconductor device includes a plurality of continuous conductive vias, wherein each continuous conductive via extends from the second major surface of the first device, through the first device, second device, third device, and fourth device to the second major surface of the fourth device. Each of the semiconductor devices may include a beveled edge at the first major surface on at least one edge of the device.
Public/Granted literature
- US20130087926A1 STACKED SEMICONDUCTOR DEVICES Public/Granted day:2013-04-11
Information query
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