Invention Grant
- Patent Title: Techniques for attenuating resonance induced impedance in integrated circuits
- Patent Title (中): 用于衰减集成电路中谐振感抗的技术
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Application No.: US13428403Application Date: 2012-03-23
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Publication No.: US09078354B2Publication Date: 2015-07-07
- Inventor: Hong Shi
- Applicant: Hong Shi
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Womble, Carlyle, Sandridge & Rice, LLP
- Main IPC: H05K1/02
- IPC: H05K1/02 ; H01L23/498 ; H01L23/50 ; H02J3/24 ; H05K1/11
Abstract:
Provided is an integrated circuit system and method for biasing the same that features bifurcating a power distribution network to provide a bias voltage to the integrated circuit system. One of the branches of the power distribution network attenuates an impedance in the power distribution network that supplies transient currents and the remaining branch supplies a substantially steady-state currents.
Public/Granted literature
- US20120176185A1 TECHNIQUES FOR ATTENUATING RESONANCE INDUCED IMPEDANCE IN INTEGRATED CIRCUITS Public/Granted day:2012-07-12
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