High density semiconductor memory devices are provided. The device may include a cell array region including a lower structure, an upper structure, and a selection structure, the selection structure being interposed between the lower and upper structures and including word lines, and a decoding circuit controlling voltages applied to the word lines. The decoding circuit may be configured to apply a first voltage to a pair of the word lines adjacent to each other and to apply a second voltage different from the first voltage to the remaining ones of the word lines, in response to word line address information input thereto.