A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures. Word lines and select lines are then formed. A 3D array of dielectric charge trapping memory cells includes stacks of NAND strings of memory cells. A plurality of switch transistors are coupled to the NAND strings, the switch transistors including gate dielectric structures wherein the gate dielectric structures are different than the dielectric charge trapping structures.