Invention Grant
- Patent Title: System and method for a cache in a multi-core processor
- Patent Title (中): 多核处理器缓存的系统和方法
-
Application No.: US13376839Application Date: 2010-06-09
-
Publication No.: US09086973B2Publication Date: 2015-07-21
- Inventor: Martin Vorbach
- Applicant: Martin Vorbach
- Applicant Address: US CA Los Gatos
- Assignee: Hyperion Core, Inc.
- Current Assignee: Hyperion Core, Inc.
- Current Assignee Address: US CA Los Gatos
- Agency: IP Spring
- Priority: EP09007607 20090609; EP09007815 20090615; EP09008861 20090707; EP10000530 20100120; EP10000689 20100125; EP10000920 20100129; EP10001453 20100212; EP10001454 20100212; EP10002122 20100302; EP10004645 20100503
- International Application: PCT/EP2010/003459 WO 20100609
- International Announcement: WO2010/142432 WO 20101216
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F9/52

Abstract:
The invention relates to a multi-core processor system, in particular a single-package multi-core processor system, comprising at least two processor cores, preferably at least four processor cores, each of said at least two cores, preferably at least four processor cores, having a local LEVEL-1 cache, a tree communication structure combining the multiple LEVEL-1 caches, the tree having at least one node, preferably at least three nodes for a four processor core multi-core processor, and TAG information is associated to data managed within the tree, usable in the treatment of the data.
Public/Granted literature
- US20120137075A1 System and Method for a Cache in a Multi-Core Processor Public/Granted day:2012-05-31
Information query