Invention Grant
- Patent Title: Cache memory with dynamic lockstep support
- Patent Title (中): 缓存内存支持动态锁步
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Application No.: US13090057Application Date: 2011-04-19
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Publication No.: US09086977B2Publication Date: 2015-07-21
- Inventor: William C. Moyer
- Applicant: William C. Moyer
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agency: Haynes and Boone, LLP
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F11/16 ; G06F12/12

Abstract:
Cache storage may be partitioned in a manner that dedicates a first portion of the cache to lockstep mode execution, while providing a second (or remaining) portion for non-lockstep execution mode(s). For example, in embodiments that employ cache storage organized as a set associative cache, partition may be achieved by reserving a subset of the ways in the cache for use when operating in lockstep mode. Some or all of the remaining ways are available for use when operating in non-lockstep execution mode(s). In some embodiments, a subset of the cache sets, rather than cache ways, may be reserved in a like manner, though for concreteness, much of the description that follows emphasizes way-partitioned embodiments.
Public/Granted literature
- US20120272007A1 CACHE MEMORY WITH DYNAMIC LOCKSTEP SUPPORT Public/Granted day:2012-10-25
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