Invention Grant
- Patent Title: Methods, systems, and articles of manufacture for implementing multiple-patterning-aware design rule check for electronic designs
- Patent Title (中): 用于实现电子设计的多图案感知设计规则检查的方法,系统和制造
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Application No.: US13840567Application Date: 2013-03-15
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Publication No.: US09087174B1Publication Date: 2015-07-21
- Inventor: Shuo Zhang , Vassilios Gerousis
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Disclosed are methods, systems, and articles of manufactures for implementing multiple-patterning-aware design rule check for an electronic design. Various embodiments identify one or more sets of multiple-exposure grids and identify or generate a data structure by using the one or more sets of grids to store design data of shape ends of various ends. Various embodiments perform constant time design rule checking by performing a constant time search process on the data structure to look up from the data structure one or more violations of one or more design rules which include at least one directional design rule. Some aspects are directed at fixing a design rule violation by using at least some grids of the one or more sets of grids.
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