Invention Grant
US09087595B2 Shielding 2-cycle half-page read and program schemes for advanced NAND flash design
有权
屏蔽用于高级NAND闪存设计的2周期半页读取和编程方案
- Patent Title: Shielding 2-cycle half-page read and program schemes for advanced NAND flash design
- Patent Title (中): 屏蔽用于高级NAND闪存设计的2周期半页读取和编程方案
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Application No.: US13867051Application Date: 2013-04-20
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Publication No.: US09087595B2Publication Date: 2015-07-21
- Inventor: Peter Wung Lee
- Applicant: Aplus Flash Technology, Inc
- Applicant Address: US CA Fremont
- Assignee: Aplus Flash Technology, Inc.
- Current Assignee: Aplus Flash Technology, Inc.
- Current Assignee Address: US CA Fremont
- Agency: Raywell Group, LLC
- Main IPC: G11C16/26
- IPC: G11C16/26 ; G11C16/04 ; G11C11/56 ; G11C16/24 ; G11C16/34

Abstract:
The present invention provides a two-cycle half-page read scheme by dividing whole NAND array bit lines (BLs) into an odd-BL group and an even-BL group. During the half-plane reading of NAND cells in the odd(even)-BL group, the half-plane even(odd)-BL group acts as the shielding BLs to protect over the odd(even)-BL string reading so that each half-page read operation is substantially reliable and free from BL coupling noise effect. Additionally, each half-page read operation is preferably divided into 3 periods: the first being a bias-condition setup period of the selected WL and remaining control signals; the second being a pre-charge period for all BLs; and the third being a half-page flash data sensing period.
Public/Granted literature
- US20130279251A1 NOVEL SHIELDING 2-CYCLE HALF-PAGE READ AND PROGRAM SCHEMES FOR ADVANCED NAND FLASH DESIGN Public/Granted day:2013-10-24
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